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hy64sd16162b series 1 revision 1.0 december. 2002 this document is a general product description and is subject to change without notice. hynix semiconductor inc. does not assume any responsibility for use of circuits described. no patent licenses are implied. document title document title 1 1 m x 16 bit low low power 1t/1c m x 16 bit low low power 1t/1c pseudo sram pseudo sram revision history revision history revision no. revision no. 1.0 history history initial draft date draft date dec. 4. ?02 remark remark preliminary
hy64sd16162b series 2 revision 1.0 december. 2002 this document is a general product description and is subject to change without notice. hynix semiconductor inc. does not assume any responsibility for use of circuits described. no patent licenses are implied. 1 1 m x 16 bit low m x 16 bit low low power 1t/1c low power 1t/1c sram sram description the hy64sd16162b is a 16mbit 1t/1c sram featured by high-speed operation and super low power consumption. the hy64sd16162b adopts one transistor memory cell and is organized as 1,048,576 words by 16bits. the hy64sd16162b operates in the extended range of temperature and supports a wide operating voltage range. the hy64sd16162b also supports the deep power down mode for a super low standby current. the hy64sd16162b delivers the high-density low power sram capability to the high-speed low power system. ? cmos process technology ? 1m x 16 bit organization ? ttl compatible and tri-state outputs ? deep power down : memory cell data hold invalid ? standard pin configuration : 48-fbga(6mmx8mm) ? data mask function by /lb, /ub ? separated i/o power supply : vddq features pin description pin name pin function pin name pin function /cs1 chip select io1~io8 lower data inputs/outputs /we write enable a0~a19 address inputs /oe output enable vdd power supply for internal circuit /lb lower byte(i/o1~i/o8) vss ground /ub upper byte(i/o9~i/o16) cs2 deep power down dnu do not use io9~io16 upper data inputs/outputs vddq power supply for i/o nc no connection pin connection (top view) /lb /oe a0 a1 a2 cs2 io9 /ub a3 a4 /cs1 io1 io10 io11 a5 a6 io2 io3 vss io12 a17 a7 io4 vdd vddq io13 dnu a16 io5 vss io15 io14 a14 a15 io6 io7 io16 a19 a12 a13 /we io8 a18 a8 a9 a10 a11 nc block diagram add input buffer pre decoder column decoder block decoder row decoder sense amp write driver data i/o buffer memory array 1,024k x 16 control logic a0 a19 io1 io8 io9 io16 /cs1 cs2 /oe /lb /ub /we product family note 1. tcs - /ub,/lb=high : chip deselect. product no. voltage [v] vdd/vddq speed trc[ns] temp. [ c] (i sb1 ,max) (i dpd ,max) (i cc2 ,max) power dissipation mode hy64sd16162b-df85i 1.8/1.8 85 -40~85 75 a 10 a 20 ma 1cs with /ub,/lb:tcs 1 HY64SD16162B-DF85E 1.8/1.8 85 -25~85 75 a 10 a 20 ma 1cs with /ub,/lb:tcs 1
hy64sd16162b series 3 revision 1.0 december. 2002 note 1. stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is stress rating only and t he functional operation of the device under these or any other conditions above those indicated in the opera tion of this specification is not implied. exposure to the absolute maximum rating conditions for extended period may affect reliability. truth table power standby /cs1 h cs2 h /we x /oe x /lb x /ub x mode deselected i/o1~i/o8 high-z i/o9~i/o16 high-z i/o pin x x l l l l l l l l l l h h h h h h h h h h x x l h h l h h l h h x x x l h x l h x l h x h l l l h h h l l l x h h h h l l l l l l deselected deselected write read output disabled write read output disabled write read output disabled high-z high-z high-z high-z d in high-z d out high-z high-z high-z d in high-z d out high-z d in d out high-z high-z high-z d in d out high-z deep power down standby active active active active active active active active active note 1. h=v ih , l=v il , x=don?t care(v il or v ih ) 2. /ub, /lb(upper, lower byte enable) these active low inputs allow individual bytes to be written or read. when /lb is low, data is written or read to the lower byte, i/o1 - i/o8. when /ub is low, data is written or read to the upper byte, i/o9 - i/o16. ordering information part number speed package hy64sd16162b-e 85 fbga hy64sd16162b-i 85 fbga power ll-part ll-part temperature e 1 i 2 note 1. e : extended temp. (-25 c~ 85 c) 2. i : industrial temp. (-40 c~ 85 c) absolute maximum ratings 1 symbol parameter rating remark v in input voltage -0.3 to vdd+0.3 unit v vdd core power supply -0.3 to 3.6 v t a ambient temperature -25 to 85 hy64sd16162b-e c t stg storage temperature -55 to 150 c p d power dissipation 1.0 w t solder ball soldering temperature & time 260?10 c?sec -40 to 85 hy64sd16162b-i c vddq i/o power supply -0.3 to 3.6 v v out output voltage -0.3 to vddq+0.3 v
hy64sd16162b series 4 revision 1.0 december. 2002 note 1. vil=-1.5v for pulse width less than 10ns undershoot is sampled, not 100% tested. recommended dc operating condition capacitance (temp = 25 c, f=1.0mhz) symbol parameter c in input capacitance(add, /cs1, cs2, /we, /oe, /ub, /lb) unit pf max. 8 condition v in =0v c out output capacitance(i/o) pf 10 v i/o =0v note : these parameters are sampled and not 100% tested symbol parameter min. vdd core supply voltage 1.8 unit v typ. - max. 2.2 v ss ground 0 v - 0 v ih input high voltage vccq*0.4 v - vdd+0.3 v il input low voltage -0.3 1 v - 0.4 vddq i/o supply voltage 1.7 v - vdd dc electrical characteristics vdd=1.8v~2.2v, vddq=1.7v~vdd, t a = -25 c to 85 c(e) / -40 c to 85 c(i) sym. parameter min. i li input leakage current -1 unit a max. 1 test condition v ss v in vdd i lo output leakage current -1 a 1 v ss v out vddq, /cs1=v ih , cs2=v ih , /oe=v ih or /we=v il i cc operating power supply current - ma 3 /cs1=v il , cs2=v ih , v in =v ih or v il , i i/o =0ma i cc1 average operating current - ma 20 /cs1=v il , cs2=v ih , v in =v ih or v il , cycle time=min. 100% duty, i i/o =0ma - ma 5 /cs1 0.2v, cs2 vdd-0.2v, v in 0.2v or v in vdd-0.2v, cycle time=1 s . 100% duty, i i/o =0ma i sb ttl standby current - ma 0.5 /cs1,cs2=v ih or /ub,/lb= v ih i sb1 standby current(cmos input) /cs1,cs2 vdd-0.2v, /ub,/lb 0.2v or /ub,/lb vdd-0.2v, otherwise cs2,/ub,/lb vdd-0.2v, /cs1 0.2v or /cs1 vdd-0.2v v ol2 output low voltage - v 0.4 i ol =0.4ma v oh2 output high voltage vddq*0.8 v vddq+0.3 i oh =-0.4ma i cc2 i dpd deep power down - a 10 cs2 v ss+ 0.2v - a 75 v ol1 output low voltage - v 0.2 i ol =0.1ma v oh1 output high voltage vddq-0.2 v vddq+0.3 i oh =-0.1ma
hy64sd16162b series 5 revision 1.0 december. 2002 ac test loads note 1. including jig and scope capacitance. ac characteristics vdd=1.8v~2.2v, vddq=1.7v~vdd, t a = -25 c to 85 c(e) / -40 c to 85 c(i), unless otherwise specified ac test conditions t a = -25 c to 85 c(e) / -40 c to 85 c(i), unless otherwise specified parameter value input pulse level 0.4 to vddq*0.8 input rising and fall time 5ns input timing reference level 0.9v output load see below output timing reference level 0.5*vddq c l 1 =50 pf d out r l =50 ohm v l =0.5*vddq z 0 =50 ohm # parameter 1 read cycle time unit ns symbol trc read cycle 2 address access time ns taa 3 chip select access time ns tacs 4 output enable to output valid ns toe 5 /lb, /ub access time ns tba 6 chip select to output in low z ns tclz 7 output enable to output in low z ns tolz 8 /lb, /ub enable to output in low z ns tblz 9 chip disable to output in high z ns tchz 10 out disable to output in high z ns tohz 11 /lb, /ub disable to output in high z ns tbhz 12 output hold from address change ns toh 13 write cycle time ns twc write cycle 14 chip selection to end of write ns tcw 15 address valid to end of write ns taw 16 /lb, /ub valid to end of write ns tbw 17 address set-up time ns tas 18 write pulse width ns twp 19 write recovery time ns twr 20 write to output in high z ns twhz 21 data to write time overlap ns tdw 22 data hold from write time ns tdh 23 output active from end of write ns tow min. 85 max. - - 85 - 85 - 30 - 85 10 - 5 - 10 - 0 10 0 10 0 10 5 - 85 - 70 - 70 - 70 - 0 - 60 - 0 - 0 10 30 - 0 - 5 - -85
hy64sd16162b series 6 revision 1.0 december. 2002 standby mode characteristics mode memory cell data standby current [ a] wait time [ s] standby valid 0 deep power down invalid 2 200 75 state diagram 1. maintain stable power for longer than 200 s. power-up sequence 1. keep cs2 low state. deep power down mode is maintained while cs2 is low state. deep power down entry sequence 1. keep cs2 high state. 2. maintain stable power for longer than 200 s. deep power down exit sequence power on power on power on wait 200 s wait 200 wait 200 s s active active active standby mode standby standby mode mode deep power down mode deep power deep power down mode down mode /cs1=v il , cs2=v ih , /ub&/lb v ih cs2=v il cs2=v il power-up sequence cs2=v ih , /cs1=v ih or /ub,/lb=v ih deep power down exit sequence deep power down entry sequence /cs2=v ih
hy64sd16162b series 7 revision 1.0 december. 2002 notes : 1. read cycle occurs whenever a high on the /we and /oe is low, while /ub and/or /lb and /cs1 and cs2 are in active status. 2. /oe = v il 3. tchz, tbhz and tohz are defined as the time at which the outputs achieve the high impedance state and tolz,tblz and tclz are defined as the time at which the outputs achieve the low impedance state. these are not referenced to output voltage levels. 4. /cs1 in high for the standby, low for active. /ub and /lb in high for the standby, low for active. timing diagram read cycle 1 ( note 1, 4 ) add /cs1 cs2 /ub, /lb /oe data out high-z vih trc taa tacs tba toe tolz (3) tblz (3) tclz (3) toh tchz (3) tbhz (3) tohz (3) data valid read cycle 2 ( note 1, 2, 4 )( cs2=vih ) add data out data valid trc previous data toh taa toh read cycle 3 ( note 1, 2, 4 )( cs2=vih ) /cs1 /ub, /lb data out data valid high-z tclz (3) tacs tchz (3)
hy64sd16162b series 8 revision 1.0 december. 2002 notes : 1. a write occurs during the overlap of low /cs1, low /we and low /ub and/or /lb. 2. twr is measured from the earlier of /cs1, /lb, /ub, or /we going high to the end of write cycle. 3. during this period, i/o pins are in the output state so that the input signals of opposite phase to the output must not be a pplied. 4. if the /cs1, /lb and /ub low transition occur simultaneously with the /we low transition or after the /we transition, outputs remain in a high impedance state. 5. /oe is continuously low (/oe=v il ) 6. q(data out) is the invalid data. 7. q(data out) is the read data of the next address. 8. twhz is defined as the time at which the outputs achieve the high impedance state. it is not referenced to output voltage levels. 9. /cs1 in high for the standby, low for active. /ub and /lb in high for the standby, low for active. 10. do not input data to the i/o pins while they are in the output state. write cycle 1 ( note 1, 4, 5, 9, 10 ) ( /we controlled ) add /cs1 cs2 /ub, /lb /we data out data in vih twc tcw tbw twp twr (2) data valid taw tas high-z tdw tdh twhz (3,8) tow (6) (7) write cycle 2 ( note 1, 4, 5, 9, 10 ) ( /cs1 controlled ) add /cs1 cs2 /ub, /lb /we data out data in vih twc tcw tbw twp twr (2) data valid taw high-z tdw tdh high-z tas
hy64sd16162b series 9 revision 1.0 december. 2002 avoid timing /we /cs1 add < trc 10us abnormal timing /we /cs1 add trc 10us avoidable timing(1) hynix 1t/1c sram has a timing which is not support ed at read operation. if your system has multiple invalid address signal shorter than trc during over 10us at read operation which showed in abnormal timing, hynix 1t/1c sram needs a normal read timi ng at least during 10us which showed in avoidable timing(1) or toggle the /cs1 to high( trc) one time at least which showed in avoidable timing(2) /we /cs1 add 10us trc avoidable timing(2) < trc
hy64sd16162b series 10 revision 1.0 december. 2002 note. 1. dimensioning and tolerancing per asme y14.5m-1994. 2. all dimensions are millimeters. 3. dimension ?d? is measured at the maximum solder ball diameter in a plane parallel to datum c. 4. primary datum c(seating plane) is defined by the crown of the solder balls. 5. this is a controlling dimension. package dimension note. 1. dimensioning and tolerancing per asme y14.5m-1994. 2. all dimensions are millimeters. 3. dimension ?d? is measured at the maximum solder ball diameter in a plane parallel to datum c. 4. primary datum c(seating plane) is defined by the crown of the solder balls. 5. this is a controlling dimension. 48ball fine pitch ball grid array package(f) unit : mm unit : mm a a b1 b1 b b c1 c1 c c d d e e e1 e1 e2 e2 r r symbol symbol - - - - 5 5 .90 .90 - - 7 7 .90 .90 0. 0. 3 3 0 0 - - - - 0.20 0.20 - - min. min. 0.75 0.75 3.75 3.75 6 6 .00 .00 5.25 5.25 8 8 .00 .00 0. 0. 3 3 5 5 1.00 1.00 0.75 0.75 0.25 0.25 - - typ typ . . - - - - 6 6 .10 .10 - - 8 8 .10 .10 0. 0. 4 4 0 0 1.10 1.10 - - 0.30 0.30 0.08 0.08 max. max. b b c c top view top view a1 corner a1 corner index area index area e e e2 e2 side view side view c c a a 5 5 r r d(diameter) d(diameter) 3 3 e1 e1 seating plane seating plane 4 4 a a b1 b1 c1 c1 bottom view bottom view a a b b c c d d e e f f g g h h 6 6 5 5 4 4 3 3 2 2 1 1 a a c/2 c/2 b/2 b/2 a1 index a1 index mark mark
hy64sd16162b series 11 revision 1.0 december. 2002 marking information index ? hysd16162b : part name hy : hynix s : power supply : vdd=1.8v~2.2v / vddq=1.7v~vdd d : tech. + classification : 1t+1c 16 : bit organization : x16 16 : density : 16m 2 : mode : 1cs with /ub,/lb;tcs b : version : 3rd generation ? c : power consumption : d ? low low power ? ss : speed : 85 ? 85ns ? t : temperature : e ? extended(-25 ~ 85 c) i ? industrial(-40 ~ 85 c) ? yy : year (ex : 02 = year 2002, 03= year 2003) ? ww : work week ( ex : 12 = work week 12 ) ? p : process code ? xxxxx : lot no. ? kor : origin country note - capital letter : fixed item - small letter : non-fixed item package marking example fbga h y s d 1 6 1 6 2 b c s s t y y w w p x x x x x k o r

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